I2C Fast Mode

Timing Constraint

Rise time requirements become more stringent as the clock frequency increases. For i2c fast mode, the maximum allowable rise time for the signal is 300 nanoseconds. This necessitates lower value pull-up resistors or active bus terminators to overcome the parasitic capacitance of the traces.

Implementation Rule

Master and slave devices must adhere to specific setup and hold times to ensure data integrity. The i2c fast mode specification introduces a shorter hold time of 600 nanoseconds for the start condition. Designers must also consider the glitch suppression requirement, which dictates that any pulse shorter than 50 nanoseconds be ignored by the receiver.

These parameters are verified using a digital storage oscilloscope during the hardware debugging phase. Bus length is generally restricted to a few inches to keep the total capacitance below the 400 picofarad limit.

Power Consumption

Higher speeds result in increased power dissipation due to the frequent charging and discharging of bus capacitance. Reducing the pull-up resistance to meet timing goals further increases the current draw when the bus is low.